The present invention relates to s semiconductor memory device, and more particularly to a technique effectively applied to a semiconductor memory device such as a DRAM etc. adopting a connection method, which is called a two cells/bit method employing a so-called one-intersection cell.
According to examinations by the inventors of the present invention, the following techniques are available for the DRAM as an example of the semiconductor memory device.
For example, with respect to the DRAM, there are an open bit-line method and a folded bit-line method as methods of connecting a sense amplifier and a bit-line pair. The former open bit-line method is one in which two bit lines to be connected to one sense amplifier are separately connected on both sides to put the sense amplifier therebetween. By the open bit-line method, a so-called one-intersection memory cell structure is formed in which memory cells MC are connected to all of the intersections between the bit-line pair BL and /BL and a word line WL. The theoretical minimum cell area of the one-intersection memory cell is 4F2 (2Fxc3x972F) in terms of a memory-cell-area representing method employing the value xe2x80x9cFxe2x80x9d of half the pitch of the word line. As a typical example of the one-intersection memory cell, the one having an area of about 6F2 (2Fxc3x973F) has been reported in the academic conference. The latter folded bit-line method is one in which two bit lines to be connected to one sense amplifier are folded and connected in the same direction relative to the sense amplifier. In the folded bit-line method, a so-called two-intersection memory cell structure is formed in which the memory cells MC are connected to half of the intersections between the bit-line pair BL and /BL and the word line WL. The theoretical minimum cell area of the two-intersection memory cell is 8F2 (4Fxc3x972F) in terms of the memory-cell-area representing method employing the value xe2x80x9cFxe2x80x9d of half the pitch of the word line.
The former open bit-line method has a high risk of obtaining error information from the memory cell since the fluctuation in a word line potential is applied to only one of the bit-line pair due to parasitic capacitance applied between the word line and the bit line. In contrast to this, the latter folded bit-line method can cancel the noise between the bit lines since the fluctuation in a word line potential (noise) is equally applied to both of the bit-line pair via the parasitic capacitance applied between the word line and the bit line. Consequently, the folded bit-line method is one suitable for the DRAM that detects and amplifies the voltage of small signal from the memory cell and, for example, is more frequently used in the DRAM of 64 kbit or lager.
Meanwhile, in DRAM employing the connection method called a two cells/bit method, there is a connection method generally called a two-intersection cellxc2x7two cells/bit method among the connection methods of the memory cells arranged at the intersections between the word lines and the bit lines. This two-intersection cellxc2x7two cells/bit method has a structure in which: a first memory cell is connected to the intersection between one of the bit-line pair and a first word line; a second memory cell is connected to the intersection between the other of the bit-line pair and a second word line; and the two memory cells correspond to one bit.
Additionally, a memory cell of the one-intersection cellxc2x7two cells/bit method is also proposed similarly. This one-intersection cellxc2x7two cells/bit method has a structure in which: a first memory cell is connected to the intersection between one of the bit-line pair and a word line; a second memory cell is connected to the intersection between the other of the bit-line pair and the same word line; and the two memory cells correspond to one bit.
Note that as techniques concerning the above-mentioned DRAM employing the one-intersection cellxc2x7two cells/bit method, there are recited, for example, Japanese Patent Laid-Open Nos. 61-34790, 55-157194, 8-222706 (U.S. Pat. No. 5,661,678 corresponding thereto), and 2001-143463 (U.S. Pat. No. 6,344,990 corresponding thereto) and Japanese Patent Publication No. 54-28252 (GB patent No. 1,502,334 corresponding thereto), etc. Also, as a technique concerning the DRAM of the two-intersection cellxc2x7two cells/bit method, Japanese Patent Laid-Open No. 7-130172 is disclosed.
Meanwhile, as a result of examination by the inventors about the techniques for the DRAM as described above, the followings have been found.
For example, in a one cell-bit method, since the signal amount on a xe2x80x9cHxe2x80x9d side is decreased depending on a refresh period, a bit-line signal amount before the amplification of the bit line cannot be used in a high-speed reading method that is read out by a direct sense method. Also, since the one-intersection cell method of the one cell/bit must employ the open bit-line method, array noises become a problem, whereby a reduction in the signal amount is an object to be solved.
As a premise of the present invention examined by the inventors, the two cells/bit method employing the above-mentioned 8F2 (4Fxc3x972F) will be described with reference to FIGS. 22 and 23. FIG. 22 is a connection diagram showing the state of the connections between the bit-line pairs orthogonal to the word lines and the sense amplifiers. FIGS. 23A and 23B are a schematic plan view and a schematic sectional view which show a twin cell structure of the memory cell, respectively.
In the two cells/bit method employing the 8F2 (4Fxc3x972F), the connections between the bit-line pairs orthogonal to the word lines and the sense amplifiers are shown in FIG. 22, wherein bit lines BL and /BL are not adjacent to each other and alternately arranged and these two lines are connected to a sense amplifier SA as a bit-line pair BL and /BL. There are a plurality of bit-line pairs BL and /BL connected in this manner, and the sense amplifiers SA are alternately connected to and arranged on the right and left ends of each bit-line pair. Further, each memory cell MC is arranged at positions corresponding to half the ones of the intersections between the bit-line pair BL and /BL and the word line WL.
The two cells/bit method employing the 8F2 (4Fxc3x972F) is, as shown in FIG. 23A, constituted to include: a plurality of folded-type bit-line pairs BL and /BL arranged in parallel to each other; a plurality of word lines WL orthogonal to the plurality of bit-line pairs BL and /BL; memory cells MC arranged at position corresponding to half the ones of the intersections between the respective bit-line pairs BL and /BL and the respective word lines WL; and the like. Also, active regions AA on the silicon substrate, in which the source, channel and drain of the transistor of the memory cell MC are formed, are formed in parallel to the bit-line pairs BL and /BL. Note that a portion corresponding to one cell of the memory cell MC is shown by the dash lines.
Further, in the sectional structure thereof, as shown in FIG. 23B, the transistor of the memory cell MC is formed on the active region AA in a P well PWEL of the silicon substrate, wherein: a gate electrode is connected to the word line WL; a source electrode is connected via a storage node contact SCT to a storage node SN to be the other of the electrode of the capacitor; and a drain electrode is connected to the bit-line pair BL and /BL via a bit contact BCT. The storage node SN is arranged at the above and opposite point thereof, and constitutes a capacitor between other plurality of capacitors and a plate PL to be one of the electrode common thereto.
Particularly, in the structure of the two cells/bit method employing the 8F2 (4Fxc3x972F), when the half pitch of the word line WL is defined as F, the pitch of the bit-line pair BL and /BL is 2F and that of the word line WL is 2F. Since one memory cell is formed with the pitch equivalent to that of the two word lines WL, the area of one cell of the memory cell is 8F2 and that of two cells/bit is 16F2. Accordingly, it becomes a problem to reduce the increase of the area of the memory cell per one bit in face of the recent advancement of higher integration.
Consequently, an object of the present invention is to provide a semiconductor memory device such as DRAM etc., which can realize high integration and ultra-high speed operation and largely reduce power consumption during a information maintaining period, by suppressing an increase in the area of a memory cell, obtaining ultra-high speed reading, and further achieving a long refresh period at the time of a self refresh.
The above and other objects and novel characteristics of the present invention will be apparent from the description of this specification and the accompanying drawings.
The typical ones of the inventions disclosed in this application will be briefly described as follows.
More specifically, a semiconductor memory device according to the present invention comprises: a plurality of folded-type bit-line pairs arranged in parallel to each other; a plurality of word lines orthogonal to these; and dynamic memory cells each composed of one transistor and one capacitor and arranged in matrix at positions corresponding to the intersections between the plurality of bit-line pairs and the plurality of word lines, wherein one electrode of the capacitor is connected to a common electrode together with those of other plurality of capacitors arranged in matrix, the other electrode thereof is connected to a source electrode of the transistor, a drain electrode of the transistor is connected to the bit-line pair, and a gate electrode thereof is connected to the word line, and wherein, in a structure in which there is connected a circuit for performing the writing of memory information to the memory cell, or the reading of memory information from the memory cell, or the refresh of the memory information of the memory cell in response to the plurality of bit-line pairs, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F when a half pitch of the word line is defined as F. Alternatively, the semiconductor memory device is one which includes a plurality of word lines not orthogonal to the plurality of bit-line pairs.
Also, a semiconductor memory device according to the present invention comprises: a plurality of dynamic memory cells which is composed of one transistor and one capacitor and is to be simultaneously selected; a bit-line pair to which the plurality of selected memory cells are connected; a sense amplifier for amplifying the potential of the bit-line pair to a predetermined xe2x80x9cHxe2x80x9d and xe2x80x9cLxe2x80x9d levels; and a pair of MOSFETs in which each of the bit-line pairs is inputted to gates thereof and drains thereof are connected to the data-line pair. In this structure, the plurality of memory cells are simultaneously selected, and signals are read out from the plurality of memory cells to the bit-line pair corresponding to the plurality of memory cells, and the signals read out to the bit-line pair are transmitted to the data line before the amplification by the sense amplifier connected to the bit-line pair.
Also, the semiconductor memory device according to the present invention is one in which: a plurality of dynamic memory cells each composed of one transistor and one capacitor are simultaneously selected; complementary signals are read out to the bit-line pair corresponding to the memory cells; and the potential of the bit-line pair is amplified to the predetermined xe2x80x9cHxe2x80x9d and xe2x80x9cLxe2x80x9d levels by the sense amplifier connected to the bit-line pair, wherein the potential of the substrate, on which the back-gate of the transistor is formed, is equal to either of the predetermined xe2x80x9cHxe2x80x9d or xe2x80x9cLxe2x80x9d level. Alternatively, the potential of the substrate, on which the back-gate of the transistor is formed, is set to be lower than the voltage of the predetermined xe2x80x9cHxe2x80x9d level or higher than that of the predetermined xe2x80x9cLxe2x80x9d level. Alternatively, the semiconductor memory device according to the present invention is one obtained by combining them, that is, one in which the precharge potential of the bit-line pair is made equal to a predetermined xe2x80x9cLxe2x80x9d or xe2x80x9cHxe2x80x9d level which is reverse to the potential of the substrate, or equal to a predetermined xe2x80x9cLxe2x80x9d or xe2x80x9cHxe2x80x9d level on the side having larger one of the potential difference between the potential of the substrate and its precharge potential.
More specifically, the semiconductor memory device according to the present invention realizes the method of the high-speed reading by using, as a two cells/bit method, the one-intersection cell which is advantageous to high integration. Note that the two-intersection cell too can be used as the two cells/bit method. However, it is not suitable for the high integration, and further the waste occurs such that two of the word lines must be simultaneously selected.
Also, in the present invention, the two memory cells of the DRAM are used as one bit and operated by the folded bit-line method in spite of the one-intersection cell. This can reduce the array noise, whereby it becomes sufficient to start up just one word line to be selected.
Furthermore, the xe2x80x9cLxe2x80x9d data are certainly stored in either of the two memory cells. The xe2x80x9cHxe2x80x9d/xe2x80x9cLxe2x80x9d signal is complementarily outputted to the bit-line pair at the time of the readout. However, in the case where the xe2x80x9cHxe2x80x9d signal is considered to be the reference of the xe2x80x9cLxe2x80x9d signal, if the xe2x80x9cLxe2x80x9d signal amount is ensured, its signal can be read out. This xe2x80x9cLxe2x80x9d data is transmitted to the main amplifier before the operation of the sense amplifier by the direct sense method, and then sensed. It is unnecessary to completely write the power voltage also in the xe2x80x9cHxe2x80x9d writing voltage. If the xe2x80x9cLxe2x80x9d data are complete, it can be easily read out. This allows for the large improvement of the refresh characteristic, the improvement in the soft error resistance, and the low-voltage high-speed operation.
Also, the occupancy of the memory cell is xc2xd due to the two cells/bit method. However, in the case of the one-intersection cell, the memory cell of about 12F2 (twice of 6F2) is obtained in a typical example. Therefore, the increase of the cell area can be suppressed to about 1.5 times as small as that of the two cells/bit method using the 8F2 cell with the same F value. Furthermore, in the ultra-high speed DRAM, the number of array divisions is increased and the occupancy of the cell becomes about 30%. Therefore, the increase of the cell area can be reduced to about 15%.
Further, if this method is applied to the two cells/bit method employing a VDL precharge method which is effective to the low-voltage operation (e.g., bit line amplitude of 1.2 V or lower), the dummy cell for the reference becomes unnecessary, thereby using the xe2x80x9cLxe2x80x9d signal amount by 100%. Also, the voltage-increasing power source (VPP) becomes unnecessary for the control of the precharge circuit, and the high-speed bit-line amplification operation can be performed even if a sense-amplifier overdrive method is not used.
As described above, according to the semiconductor memory device of the present invention, (i) even if the xe2x80x9cHxe2x80x9d data is reduced by the refresh, the xe2x80x9cLxe2x80x9d data is left. Therefore, it is also possible to operate the main amplifier by the direct sense of the xe2x80x9cLxe2x80x9d signal. (ii) The readout of the xe2x80x9cLxe2x80x9d data is more rapid than that of the xe2x80x9cHxe2x80x9d data, thereby allowing for the high-speed and stable operation. (iii) Since the full writing of the xe2x80x9cHxe2x80x9d data is unnecessary, the word-line-voltage increasing level can be reduced. (iv) The current consumption in the VPP voltage-increasing circuit can be reduced and the noise generated at the time of operating the VPP generator circuit can be reduced. (v) The bit-line pair has a completely symmetric structure owing to the operation of the folded bit-line method and the noise in the array including the non-selected word-line noise can be completely canceled even in the case of the one-intersection memory cell. (vi) It is possible to largely improve the period of the refresh time and the soft error resistance by the readout of the xe2x80x9cLxe2x80x9d data.
As a result, the xe2x80x9cLxe2x80x9d data are certainly stored in either of the cells in the two cells/bit method. Accordingly, data on the side of the xe2x80x9cLxe2x80x9d has the readout speed higher than the xe2x80x9cHxe2x80x9d data, thereby allowing for ensuring the signal amount more stably. Additionally, in the operation of the folded bit-line method, the bit lines are arranged on the same array side, thereby allowing for canceling the substrate noises and the plate noises. Furthermore, since the wrap-around noises form the non-selected word line is also caused on the bit-line pair, the loss of the signal amount is prevented. Due to the advantages as described above, it is possible to obtain the stable bit-line signal on the xe2x80x9cLxe2x80x9d side. If it is directly read out, the data can be transmitted to the output buffer before the driving of the bit line.